1. Technical Field
The embodiments described herein relate to a semiconductor circuit technology and, more particularly, to a delay circuit of a delay locked loop in a semiconductor integrated circuit and a method for controlling the same.
2. Related Art
A delay locked loop (DLL) is a circuit for synchronizing a clock signal supplied from an external circuit with a clock signal used in an internal circuit of a conventional semiconductor memory apparatus. A conventional delay locked loop includes a delay circuit. The delay circuit changes a delay time of a clock signal, which is input from the external circuit, in response to a control signal, which is generated within the delay locked loop, and outputs the delayed clock signal. Conventional delay circuits are implemented by a dual delay line or a single delay line.
As shown in FIG. 1, a conventional delay circuit includes a dual delay line (1 and 2) and a phase mixer 3.
The dual delay line (1 and 2) delays and outputs a clock signal in response to control signals generated by shift registers in a delay locked loop. The delay time is determined by the number of unit delayers activated by the control signals.
The phase mixer 3 mixes two signals that are output by the dual delay line (1 and 2) to output an output signal ‘CLK_out’.
A driving circuit is required to drive signals input onto the two delay lines. However, a conventional driving circuit consumes a large amount of current and causes a large amount of noise. In addition, since the driving circuit occupies a large area, it limits integration.
Referring to FIG. 2, a delay circuit using a single delay line includes a plurality of delayers 210 to 210 to 214 and a plurality of switches 215 to 219. The reference numeral 220 designate a multiplexer and 230 a phase mixer. U.S. Pat. No. 7,016,452 discloses a conventional delay circuit using the single delay line.
A delay circuit using the single delay line, such as that disclosed in U.S. Pat. No. 7,106,452, needs a large number of switches 215 to 219 to control the outputs of the plurality of delayers 210 to 210 to 214. As a result, the circuit area becomes is increased and the circuit is unstable in coupling capacitance. In the delay circuit using the single delay line, the most critical issue is to increase the generation of signal distortion and then it is difficult to operate in a high-frequency.